1. Field of the Invention
The present invention relates to an output structure for a substrate electric potential in a semiconductor device in which an output region for the substrate electric potential is enclosed with a field insulating layer formed by LOCOS (selective oxidation), and a method of producing the output structure of the substrate electric potential.
2. Prior Art
As shown in FIG. 3, the structure of a conventional semiconductor device, in particular of an output region of the substrate electric potential, comprises, for example an element segregation region 23 selectively formed in an N-type epitaxial layer 22 formed on a P-type silicon substrate 21, a field insulating layer 24 selectively formed with LOCOS at a portion corresponding to the element segregation region 23 on the epitaxial layer 22, and a P-type impurity diffusion region 26 (exhibited in dotted line) formed on a surface of an output region 25 enclosed by the field insulating layer and passing through the epitaxial layer 22.
In order to reduce a diffusion amount in a cross direction, to improve the precision in the pattern consistency concerning photolithography technique or the like, and to optimize an epitaxial layer (for example, optimization of concentration and thickness) in relation to the fine designing of semiconductor device, variable processes regarding semiconductor devices and particularly thermal treatment for diffusion of impurities has recently been carried out at low temperature. Such treatment at low temperature simultaneously means the reduction in the diffusion depth xj of the impurities.
However, since the diffusion region 26 in the output region for the substrate electric potential shown in FIG. 3 requires diffusion into a deeper depth down to dashed line 26-1, a diffusion depth xj.sub.1 cannot be obtained even through the reduction in the thickness of the epitaxial layer 22. A diffusion depth of the diffusion region formed on a surface of said output region 25 results in a depth xj.sub.2, shown by reference numeral 26-2. Accordingly, the epitaxial layer 22 cannot be passed through, as is exhibited in solid lines, causing inconvenience such as difficulty in the output of the substrate electric potential.
As shown in FIG. 4, there is thus provided a method comprising forming in preliminary fashion a diffusion region (pseudo embedding region) 27 of a P-type identical to a type of an element segregation region 23 under an output region 25 for the substrate electric potential at the time of forming the element segregation region 23, and constituting a diffusion region 26 and the above-mentioned diffusion region 27 so that they might join together when the diffusion region 26 is formed on the surface of the contact region 25 of the substrate electric potential in the following process. However, the above-mentioned method involves the inconvenience of a complex fabrication process as in conventional cases. That is, the method requires ion implantation and thermal treatment at high temperature for forming the element segregation region 23 and the diffusion region 27, and it also requires ion implantation and thermal treatment at low temperature for forming the diffusion region 26, involving the inconvenience of a complex process and a high fabrication cost.